PDN Impedance and Noise Simulation of 3D SiP with a Widebus Structure

A 3D stacked system-in-package (SiP) with a widebus structure is expected to have large SSO noise compared with conventional memory devices with small number of IOs. Then, Power supply impedances for a 3D SiP with a widebus structure has been investigated including stacked chips, an organic substrate, and a board. The 3D SiP consisted of 3 stacked chips and an organic substrate. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic substrate, whose size was 26 mm by 26mm. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.) and confirmed by measurement. Then, the PDN impedance for the organic substrate was extracted by using SIwave (Ansys Inc.) and also confirmed by measurement. Finally, the total PDN impedance seen from each chip was synthesized to estimate the power supply disturbance due to the anti-resonance peak, and power supply noise level was estimated by establishing a whole SPICE model.