Impact of Single Charged Gate Oxide Defects on the Performance and Scaling of Nanoscaled FETs

被引：61

作者：

Franco, J. ^{[1
]}

Kaczer, B. ^{[1
]}

Toledano-Luque, M. ^{[1
]}

Roussel, Ph J. ^{[1
]}

Mitard, J. ^{[1
]}

Ragnarsson, L. -A. ^{[1
]}

Witters, L. ^{[1
]}

Chiarella, T. ^{[1
]}

Togo, M. ^{[1
]}

Horiguchi, N. ^{[1
]}

Groeseneken, G. ^{[1
]}

Bukhori, M. F. ^{[2
]}

Grasser, T. ^{[3
]}

Asenov, A. ^{[4
,5
]}

机构：

[1] IMEC, Louvain, Belgium

[2] Univ Kebangsaan Malaysia, Bangi, Malaysia

[3] Inst Microelectron, Vienna, Austria

[4] Univ Glasgow, Glasgow, Lanark, Scotland

[5] Gold Standard Simulat Ltd, Glasgow, Lanark, Scotland

来源：

2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2012年

基金：

欧盟第七框架计划;

关键词：

finFET; Nanoscale; Negative Bias Temperature Instability; pMOSFETs; SiGe; Time-Dependent Variability; NBTI DEGRADATION;

D O I：

10.1109/IRPS.2012.6241841

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET I-D-V-G characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

引用

页数：6

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