A Novel Multi-Bit Sigma-Delta Modulator using an Integrating SAR Noise-Shaped Quantizer

This paper presents a multi-bit Sigma-Delta modulator using a novel integrating SAR noise-shaped quantizer. The proposed quantizer is similar to an integrating ADC where the charge stored in the integration phase is afterwards measured with a SAR algorithm. The charge residue present at the integrator after a measurement cycle is stored for the next conversion, providing first-order noise shaping. In this fashion, not only the flash quantizer is removed and an extra order of noise shaping is achieved, but also all the capacitive loading of the multi bit flash quantizer is replaced by a single comparator. The modulator order can be increased by the addition of more integrating stages. Furthermore, this technique extracts the quantization error directly in analog and time domains. This quantization error can be used in different loop architectures such as the MASH or time-interleaved noise-coupled structures, without the need for an extra DAC. Thus making this architecture a power and area efficient solution for converters of low or medium speeds. As an example, the system level performance of a second order multi-bit Sigma-Delta modulator with the proposed architecture has been evaluated.