Quantum simulation of device characteristics of silicon nanowire FETs

被引:38
作者
Shin, Mincheol [1 ]
机构
[1] Informat & Commun Univ, Sch Engn, Taejon 305714, South Korea
关键词
device simulation; MOSFET; quantum transport;
D O I
10.1109/TNANO.2007.891819
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A quantum simulation of silicon nanowire field-effect transistors has been performed in the frame work of the effective mass theory, where the three-dimensional Poisson equation was solved self-consistently with the mode-space nonequilibrium Green's function equations in the ballistic transport regime. The dependence of the device performance on the gate length and width for three types of gate configuration has been studied, focusing on the contribution of the tunneling current to the total current. The effects of gate underlap and the corner rounding of silicon body on the device performance have been also investigated quantitatively, leading to the conclusions that the gate underlap is an important factor in improving the subthreshold characteristics of the device, but the corner rounding of silicon body is not a significant factor, especially for devices with silicon body width of a few nanometers.
引用
收藏
页码:230 / 237
页数:8
相关论文
共 13 条
[1]   Leakage and performance of zero-Schottky-barrier carbon nanotube transistors [J].
Alam, K ;
Lake, RK .
JOURNAL OF APPLIED PHYSICS, 2005, 98 (06)
[2]   3D quantum modeling and simulation of multiple-gate nanowire MOSFETs [J].
Bescond, M ;
Nehari, K ;
Autran, JL ;
Cavassilas, N ;
Munteanu, D ;
Lannoo, M .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :617-620
[3]   Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs [J].
Colinge, JP ;
Park, JW ;
Xiong, W .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (08) :515-517
[4]   High performance silicon nanowire field effect transistors [J].
Cui, Y ;
Zhong, ZH ;
Wang, DL ;
Wang, WU ;
Lieber, CM .
NANO LETTERS, 2003, 3 (02) :149-152
[6]   Influence of band-structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic study [J].
Nehari, K ;
Cavassilas, N ;
Autran, JL ;
Bescond, M ;
Munteanu, D ;
Lannoo, M .
PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, :229-232
[7]   Multiple-gate SOI MOSFETs: Device design guidelines [J].
Park, JT ;
Colinge, JP .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (12) :2222-2229
[8]   Efficient simulation of silicon nanowire field effect transistors and their scaling behavior [J].
Shin, Mincheol .
JOURNAL OF APPLIED PHYSICS, 2007, 101 (02)
[9]   Nanoscale FinFETs with gate-source/drain underlap [J].
Trivedi, V ;
Fossum, JG ;
Chowdhury, MM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (01) :56-62
[10]   On the validity of the parabolic effective-mass approximation for the I-V calculation of silicon nanowire transistors [J].
Wang, J ;
Rahman, A ;
Ghosh, A ;
Klimeck, G ;
Lundstrom, M .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (07) :1589-1595