Simulated device design optimization to reduce the floating body effect for sub-quarter micron fully depleted SOI-MOSFETs

被引:0
|
作者
Koh, R
Mogami, T
Kato, H
机构
关键词
SOI; MOSFET; floating body effect; simulation; applicable voltage;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2 mu m Fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.
引用
收藏
页码:893 / 898
页数:6
相关论文
共 33 条
  • [31] Gate-induced floating-body effect (GIFBE) in fully depleted triple-gate n-MOSFETs
    Na, K. -I.
    Cristoloveanu, S.
    Bae, Y. -H.
    Patruno, P.
    Xiong, W.
    Lee, J. -H.
    SOLID-STATE ELECTRONICS, 2009, 53 (02) : 150 - 153
  • [32] Analysis of the threshold voltage adjustment and floating body effect suppression for 0.1 mu m fully depleted SOI-MOSFET
    Koh, R
    Matsumoto, H
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1997, 36 (3B): : 1563 - 1568
  • [33] Structure and process parameter optimization for sub-10nm gate length fully depleted N-type SOI MOSFETs by TCAD modeling and simulation
    Jin, Yawei
    Ma, Lei
    Zeng, Chang
    Dandu, Krishnanshu
    Barlage, Doug William
    TRANSISTOR SCALING- METHODS, MATERIALS AND MODELING, 2006, 913 : 39 - +