High-Level System-on-Chip Simulator

A high-level simulation is a significant part of the multicore system-on-chip (SoC) software development process. It allows executing programs and performing functional debugging on the high-level model of the SoC without going into details of SoC heterogeneous cores: a specific command set, a processes interaction, a communication system specifics etc. The high-level simulation is also a necessary part of the SW/HW co-design tool flows. This paper presents the developed high-level SoC simulator. This simulator allows executing coarse-grain programs in the configurable SoC-style distributed environment with heterogeneous processing elements and an interconnection. A parallel data-processing workload (SoC program) is been defining as a scheme of interacting processes with a C/C++ implementation and specific characteristics. Various simulation statistics allows investigating characteristics of a developed program (maximal parallelism levels, computation space requirements, amounts of interaction data), abilities of SoC architecture to perform such workload (processing elements and communication system occupation, buffers size distribution, queues etc.) and characteristics of program execution (processing time, latencies, constraints).