TSV Modeling and Thermal Analysis Based on 3D Package

被引：0
|
作者：
Tian Wenchao [1 ]
Wang Wenlong [1 ]
Wang Hongming [1 ]
机构：
[1] Xidian Univ, Sch Electromech Engn, Xian 710071, Shaanxi, Peoples R China
来源：
2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012) | 2012年
关键词：
TSV; 3D lamination; electronic packaging;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
TSV heat models with different pitches, straight through holes and circular truncated cones are established. Simulation results are obtained, and compared with wire bonding results. The conclusion that the heat dissipation effect of TSV technology is better than that of wire bonding technology is obtained. Heat dissipation effect has nothing to do with TSV shape under the same TSV pitches.
引用
收藏
页码：545 / 547
页数：3
相关论文
共 50 条
  • [1] Numerical Modeling of the Thermal Performance of 3D SiP with TSV
    Pan, Kailin
    Huang, Jing
    Liu, Jing
    Zhu, Weitao
    Ren, Guotao
    MANUFACTURING PROCESS TECHNOLOGY, PTS 1-5, 2011, 189-193 : 1610 - 1613
  • [2] 3D package thermal analysis and thermal optimization
    Deng, Yaohui
    Liu, Peisheng
    Zhang, Zhao
    Jin, Jiajie
    Xu, Pengpeng
    Yan, Lei
    CASE STUDIES IN THERMAL ENGINEERING, 2024, 64
  • [3] Thermal resistance analysis for a high power 3D integrated RF Module based on TSV interposer
    Ma, Xinxin
    Ma, Shenglin
    Gong, Dan
    Wang, Mengcheng
    Jin, Yufeng
    Wang, Wei
    Chen, Jing
    He, Shuwei
    Hu, Liulin
    Zhou, Bin
    2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 406 - 412
  • [4] Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3D ICs
    Jung, Moongon
    Pan, David Z.
    Lim, Sung Kyu
    2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 317 - 326
  • [5] A Comprehensive Platform for Thermal Studies in TSV-based 3D Integrated Circuits
    Souare, P. M.
    Coudrain, P.
    Colonna, J. P.
    Fiori, V.
    Farcy, A.
    de Crecy, F.
    Borbely, A.
    Ben-Jamaa, H.
    Laviron, C.
    Gallois-Garreignot, S.
    Giraud, B.
    Hotellier, N.
    Franiatte, R.
    Dumas, S.
    Chancel, C.
    Riviere, J. -M.
    Pruvost, J.
    Cheramy, S.
    Tavernier, C.
    Michailos, J.
    Le Pailleur, L.
    2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2014,
  • [6] Etching Process Development for 3D Wafer Level Via Last TSV Package
    Ren, Yulong
    Geng, Fei
    Sun, Peng
    Sun, Yanan
    Sima, Ge
    2017 18TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2017, : 296 - 300
  • [7] Analysis of RF transmission performance of 3D TSV interposer
    Wang, Zhengduo
    Lang, Liang
    Wu, Fengshun
    Wang, Bo
    2018 19TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2018, : 937 - 940
  • [8] Front to backside alignment for TSV based 3D integration
    Windrich, Frank
    Schenke, Andreas
    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
  • [9] Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs
    Kaibartta, Tanusree
    Biswas, G. P.
    Das, Debesh Kumar
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2020, 36 (02): : 239 - 253
  • [10] Simulation in 3D Integration and TSV
    Weide-Zaage, K.
    Moujbani, A.
    Kludt, J.
    2014 IEEE 5TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS), 2014,
12345