Two-stage ADC-based ROICs for 25 μm-pitch cryogenic infrared focal plane array

被引：4

作者：

Niu, Yuze ^{[1
,2
]}

Huang, Zhaofeng ^{[1
,2
]}

Lu, Wengao ^{[1
,2
]}

Lu, Huaixi ^{[1
]}

Chen, Guangyi ^{[1
]}

Zhang, Yacong ^{[1
]}

Chen, Zhongjian ^{[1
]}

机构：

[1] Peking Univ, Dept Microelect, Key Lab Microelect Devices & Circuits, Beijing 100871, Peoples R China

[2] Peking Univ, Informat Technol Inst Tianjin Binhai, Tianjin 300452, Peoples R China

来源：

ELECTRONICS LETTERS | 2019年 / 55卷 / 02期

基金：

中国国家自然科学基金;

关键词：

analogue-digital conversion; focal planes; readout electronics; cryogenic electronics; low-power electronics; comparators (circuits); digital integrated circuits; size; 25; 0; mum; 18; power; 50; muW; infrared focal plane arrays; low-power-consumption comparator structure; PFM-based pixel-level ADC; power consumption; 25 m-pitch cryogenic; focal plane array; 1P6M CMOS process; two stage ADC-based ROIC; two-stage ADC-based digital readout integrated circuits; fine quantify module; charge handling capability;

D O I：

10.1049/el.2018.5643

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power, high-linearity, high-charge handling capability two-stage ADC-based 384 x 288 size digital readout integrated circuits (ROIC) for infrared focal plane arrays are presented. A novel high-speed, low-power-consumption comparator structure is proposed in this work. Moreover, the two-stage ADC combines the pulse frequency modulation (PFM)-based pixel-level ADC and fine quantify module, improving the charge handling capability and the linearity of the readout circuit. The ROIC with 25 mu m pixel pitch has been realised in 0.18 mu m 1P6M CMOS process. The power consumption of the two-stage ADC is 50 mu W. The charge handling capability of the pixel is 2.3 Ge- and the non-linearity of the proposed circuit is 0.09%.

引用

页码：72 / +

页数：2

共 4 条

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