Fast modulo 2k-1 multiplication

被引：0
|
作者：
Jablonski, Janusz [1 ]
Dylewski, Robert [1 ]
机构：
[1] Uniwersytet Zielonogorski, Wydzialu Matemat Informatyki & Ekonometrii, PL-65516 Zielona Gora, Poland
来源：
PRZEGLAD ELEKTROTECHNICZNY | 2012年 / 88卷 / 08期
关键词：
modulo multiplier; CSA; partial products; Wallace tree;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this article represents the author's conception of multiplier modulo 2k-1, leaning on reducer 4:2. The proposed solution gives the possibility of detecting and the quicker marking - the less logical levels, special cases of multiplication, connected with specific values sums of partial products. This presented solution and circuit can accelerate parallel multplier - built on Wallace tree addition. (Fast modulo 2k-1 multiplication).
引用
收藏
页码：145 / 147
页数：3
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