Automatic Addition of Reset in Asynchronous Sequential Control Circuits

被引:0
|
作者
Vij, Vikas S. [1 ]
Stevens, Kenneth S. [1 ]
机构
[1] Univ Utah, Salt Lake City, UT 84112 USA
来源
2013 IFIP/IEEE 21ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2013年
关键词
BURST-MODE CIRCUITS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Asynchronous finite state machines (AFSMs) usually require initialization to place them in a desired starting state. This normally occurs by toggling a reset signal upon power-up. This paper presents an algorithm to automatically generate power-up reset circuitry thus adding reset to an AFSM after technology mapping. This approach is independent of design methodology since it is applied to a gate netlist. The algorithm ensures all combinational cycles and primary outputs in the circuit are initialized. Options exist in reset generation to minimize the power or performance impact on the AFSM. Results are reported for applying this algorithm to designs of varying size and complexity.
引用
收藏
页码:374 / 379
页数:6
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