Improved Sub-threshold Slope in RF Vertical MOSFETS using a Frame Gate Architecture

被引：2

作者：

Hakim, M. M. A. ^{[1
]}

Uchino, T. ^{[1
]}

White, W. R. ^{[1
]}

Ashburn, P. ^{[1
]}

Tan, L. ^{[2
]}

Buiu, O. ^{[2
]}

Hall, S. ^{[2
]}

机构：

[1] Univ Southampton, Southampton SO17 1BJ, Hants, England

[2] Univ Liverpool, Dept EEE, Liverpool L69 3GJ, Merseyside, England

来源：

ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2008年

基金：

英国工程与自然科学研究理事会;

关键词：

D O I：

10.1109/ESSDERC.2008.4681707

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80mV/decade and DIBL of 30-35mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of I 10 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch.

引用

页码：95 / +

页数：2

共 9 条

[1] Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs [J].

Gili, Enrico ;

Uchino, Takashi ;

Al Hakim, Mohammad M. ;

de Groot, C. H. ;

Buiu, Octavian ;

Hall, Steve ;

Ashburn, Peter .

IEEE ELECTRON DEVICE LETTERS, 2006, 27 (08) :692-695

[2]

Hergenrother J. M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P75, DOI 10.1109/IEDM.1999.823850

[3] A novel 50 nm vertical MOSFET with a dielectric pocket [J].

Jayanarayanan, S. K. ;

Dey, S. ;

Donnelly, J. P. ;

Banerjee, S. K. .

SOLID-STATE ELECTRONICS, 2006, 50 (05) :897-900

[4] Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation [J].

Kunz, VD ;

Uchino, T ;

de Groot, CH ;

Ashburn, P ;

Donaghy, DC ;

Hall, S ;

Wang, Y ;

Hemment, PLF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (06) :1487-1493

[5] An ultrathin vertical channel MOSFET for sub-100-nm applications [J].

Liu, HT ;

Xiong, ZB ;

Sin, JKO .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (05) :1322-1327

[6] Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching [J].

Masahara, M ;

Liu, YX ;

Hosokawa, S ;

Matsukawa, T ;

Ishii, K ;

Tanoue, H ;

Sakamoto, K ;

Sekigawa, T ;

Yamauchi, H ;

Kanemaru, S ;

Suzuki, E .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (12) :2078-2085

[7]

MOERS J, 2003, 33 C EUR SOL STAT DE, P143

[8] Sub-100-nm vertical MOSFET with threshold voltage adjustment [J].

Mori, K ;

Duong, A ;

Richardson, WF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (01) :61-66

[9] Short-channel vertical sidewall MOSFETs [J].

Schulz, T ;

Rösner, W ;

Risch, L ;

Korbel, A ;

Langmann, U .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (08) :1783-1788

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