Study on Race and Hazard of Combinational Logic Circuit

被引：0
|
作者：
Wang Xiuling [1 ]
Wang Haocheng [1 ]
机构：
[1] Inner Mongolia Univ Technol, Coll Informat Engn, Hohhot 010051, Inner Mongolia, Peoples R China
来源：
INTELLIGENCE COMPUTATION AND EVOLUTIONARY COMPUTATION | 2013年 / 180卷
关键词：
combinational logic circuit; race hazard; detect; elimination; SWITCHING CIRCUITS;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The reasons and types, detection methods, elimination and simulation of the race and hazard phenomenon in combination logic circuit are introduced and analyzed. The removing methods of race and hazard are pointed out with examples.
引用
收藏
页码：281 / 286
页数：6
相关论文
共 50 条
  • [21] Category recognition system using two ultrasonic sensors and combinational logic circuit
    Moritake, Y
    Hikawa, H
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 2005, 88 (07): : 33 - 42
  • [22] Inverse-Designed Metamaterials for On-Chip Combinational Optical Logic Circuit
    Tan Q.
    Qian C.
    Chen H.
    Progress in Electromagnetics Research, 2023, 176 : 55 - 65
  • [23] Inverse-Designed Metamaterials for On-Chip Combinational Optical Logic Circuit
    Tan, Qingze
    Qian, Chao
    Chen, Hongsheng
    PROGRESS IN ELECTROMAGNETICS RESEARCH-PIER, 2023, 176 : 55 - 65
  • [24] A CMOS COMBINATIONAL CIRCUIT-DESIGN METHOD USING MIXED LOGIC CONCEPTS
    HUDSON, WB
    BEASLEY, JS
    STEELMAN, JE
    IEEE TRANSACTIONS ON EDUCATION, 1995, 38 (03) : 266 - 273
  • [25] A Novel Method for Power Analysis Based on Combinational Logic in Block Cipher Circuit
    GUO Zheng
    GU Dawu
    YUAN Kan
    LIU Junrong
    HE Yuming
    ChineseJournalofElectronics, 2014, 23 (01) : 151 - 156
  • [26] Computing the soft error rate of a combinational logic circuit using parameterized descriptors
    Rao, Rajeev R.
    Chopra, Kaviraj
    Blaauw, David T.
    Sylvester, Dennis M.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (03) : 468 - 479
  • [27] A Novel Method for Power Analysis Based on Combinational Logic in Block Cipher Circuit
    Guo Zheng
    Gu Dawu
    Yuan Kan
    Liu Junrong
    He Yuming
    CHINESE JOURNAL OF ELECTRONICS, 2014, 23 (01) : 151 - 156
  • [28] Automatic Abstraction of Combinational Logic Circuit from Scanned Document Page Images
    Ramanath Datta
    Sekhar Mandal
    Samit Biswas
    Pattern Recognition and Image Analysis, 2019, 29 : 212 - 223
  • [29] Determination of combinational logic circuit reliability through generation of fault diagnosis tests
    Dokouzgiannis, S.P.
    Kontoleon, J.M.
    Microelectronics Reliability, 1988, 28 (04) : 541 - 545
  • [30] Combinational circuit optimization
    Iman, S
    Pedram, M
    LOW POWER DESIGN IN DEEP SUBMICRON ELECTRONICS, 1997, 337 : 267 - 320
12345