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- [31] QED Post-Silicon Validation and Debug: Frequently Asked Questions 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 478 - 482
- [32] Interconnection Fabric Design for Tracing Signals in Post-Silicon Validation DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2009, : 352 - 357
- [34] Quick Detection of Difficult Bugs for Effective Post-Silicon Validation 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 561 - 566
- [35] Learn to Tune: Robust Performance Tuning in Post-Silicon Validation 2023 IEEE EUROPEAN TEST SYMPOSIUM, ETS, 2023,
- [36] A Methodology for SAT-based Electrical Error Debugging during Post-silicon Validation 2019 32ND INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2019 18TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2019, : 389 - 394
- [37] Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip 2021 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2021), 2021, : 248 - 253
- [38] Trace Buffer Attack: Security versus Observability Study in Post-Silicon Debug 2015 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2015, : 355 - 360
- [39] Global Transaction Ordering in Network-on-Chips for Post-Silicon Validation 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2011, : 284 - 289
- [40] Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware IECON 2020: THE 46TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2020, : 3836 - 3840