Calibration of SAR Analog-to-Digital Converters for Expanding the Sampling Rate Range

被引：0
|
作者：
Naghibzadeh, Abbas [1 ]
Rezaee-Dehsorkh, Hamidreza [1 ]
Ravanshad, Nassim [1 ]
机构：
[1] Sadjad Univ Technol, Dept Elect Engn, Mashhad, Iran
来源：
2017 29TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (ICM) | 2017年
关键词：
SAR ADC; Digital Calibration; Capacitive DAC; Leakage Current; Compensation; ADC;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Successive approximation analog to digital converters (SARs) are widely used in electronic circuits because of good performance from the power consumption, resolution and speed points of view. Leakage currents and DAC incomplete settling limits the performance of these ADCs in low and high sampling rates respectively. This limits the range of the sampling rate in which a SAR ADC can be used and so the usage of this ADC in multi-purpose SoCs. In this paper a background calibration technique is used in order to improve the range of the SAR ADC sampling rate. It is shown that by utilizing this technique, the sampling rate can be improved in a range of from 50 kHz to 1 MHz for a 10-bit SAR ADC with ENOB > 9 bit which is designed and simulated in 90 nm CMOS technology with a 1.2 V supply voltage.
引用
收藏
页码：326 / 329
页数：4
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