A novel three-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell

被引：9

作者：

Aritome, Seiichi ^{[1
]}

Whang, SungJin ^{[1
]}

Lee, KiHong ^{[1
]}

Shin, DaeGyu ^{[1
]}

Kim, BeomYong ^{[1
]}

Kim, MinSoo ^{[1
]}

Bin, JinHo ^{[1
]}

Han, JiHye ^{[1
]}

Kim, SungJun ^{[1
]}

Lee, BoMi ^{[1
]}

Jung, YoungKyun ^{[1
]}

Cho, SungYoon ^{[1
]}

Shin, ChangHee ^{[1
]}

Yoo, HyunSeung ^{[1
]}

Choi, SangMoo ^{[1
]}

Hong, Kwon ^{[1
]}

Park, SungKi ^{[1
]}

Hong, SungJoo ^{[1
]}

机构：

[1] SK Hynix, R&D Div, Inchon 467701, Gyeonggi Do, South Korea

来源：

SOLID-STATE ELECTRONICS | 2013年 / 79卷

关键词：

3D; Floating gate; NAND; Flash memory; ULTRA-HIGH DENSITY;

D O I：

10.1016/j.sse.2012.07.005

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel three-dimensional (3D) Dual Control gate with Surrounding Floating gate (DC-SF) NAND flash cell has been successfully developed. The DC-SF cell consists of a surrounding floating gate with stacked dual control gates. With this structure, high coupling ratio, low voltage cell operation, and wide P/E window (9.2 V) can be obtained. Moreover, negligible FG-FG coupling interference (12 mV/V) is achieved due to the control-gate shield effect. As a result, DC-SF NAND flash cell can overcome the problems of SONOS-based 3D NAND flash. It is proposed that 3D DC-SF NAND flash cell is the most promising candidate for 1 Tb and beyond, with stacked multi bit FG cell (2-4 bits/cell). (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：166 / 171

页数：6

共 23 条

[1] Novel 3-Dimensional Dual Control-Gate with Surrounding Floating-Gate (DC-SF) NAND Flash Cell for 1Tb File Storage Application
Whang, SungJin
Lee, KiHong
Shin, DaeGyu
Kim, BeomYong
Kim, MinSoo
Bin, JinHo
Han, JiHye
Kim, SungJun
Lee, BoMi
Jung, YoungKyun
Cho, SungYoon
Shin, ChangHee
Yoo, HyunSeung
Choi, SangMoo
Hong, Kwon
Aritome, Seiichi
Park, SungKi
Hong, SungJoo
2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST, 2010,
[2] New read scheme of variable vpass-read for dual control gate with surrounding floating gate (DC-SF) NAND flash cell
Yoo H.
Choi E.
Joo H.
Cho G.
Park S.
Aritome S.
Lee S.
Hong S.
2011 3rd IEEE International Memory Workshop, IMW 2011, 2011,
[3] Impact of Control-Gate and Floating-Gate Design on the Electron-Injection Spread of Decananometer NAND Flash Memories
Compagnoni, Christian Monzio
Miccoli, Carmine
Lacaita, Andrea L.
Marmiroli, Andrea
Spinelli, Alessandro S.
Visconti, Angelo
IEEE ELECTRON DEVICE LETTERS, 2010, 31 (11) : 1196 - 1198
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Lee, JD
Hur, SH
Choi, JD
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (05) : 264 - 266
[5] Floating-Gate Coupling Canceller for Multi-Level Cell NAND Flash
Park, Donghyuk
Lee, Jaejin
IEEE TRANSACTIONS ON MAGNETICS, 2011, 47 (03) : 624 - 628
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Seo, Moon-Sik
Endoh, Tetsuo
JAPANESE JOURNAL OF APPLIED PHYSICS, 2012, 51 (02)
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Seo, Moon-Sik
Endoh, Tetsuo
Japanese Journal of Applied Physics, 2012, 51 (2 PART 2)
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Seo, Moon-Sik
Lee, Bong-Hoon
Park, Sung-Kye
Endoh, Tetsuo
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (08) : 2078 - 2084
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Zhang, Yintong
Xu, Zhaozhao
Liang, Xuanming
Wu, Zhitao
Zhou, Yang
Xu, Gavin
Fang, Ziquan
Liu, Donghua
Li, Alex
Qian, Wensheng
CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,
[10] Three-dimensional self-consistent simulation of silicon quantum-dot floating-gate flash memory device
Thean, A
Leburton, JP
IEEE ELECTRON DEVICE LETTERS, 1999, 20 (06) : 286 - 288

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