共 27 条
- [21] Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC PROCEEDINGS OF 2020 INTERNATIONAL CONFERENCE ON INNOVATIVE TRENDS IN COMMUNICATION AND COMPUTER ENGINEERING (ITCE), 2020, : 299 - 302
- [23] Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization INTERNATIONAL JOURNAL OF ENGINEERING, 2021, 34 (12):
- [24] Design of area efficient single bit comparator circuit using quantum dot cellular automata and its digital logic gates realization International Journal of Engineering, Transactions B: Applications, 2021, 34 (12):
- [26] An Area-Efficient and Low-Power Comparator for Type-III Compensated Voltage-Mode Control DC-DC Buck Converter in 65nm CMOS Technology Process ISCIT 2019: PROCEEDINGS OF 2019 19TH INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES (ISCIT), 2019, : 113 - 117