Impact of three-dimensional architectures on interconnects in gigascale integration

被引:46
|
作者
Joyner, JW [1 ]
Venkatesan, R [1 ]
Zarkesh-Ha, P [1 ]
Davis, JA [1 ]
Meindl, JD [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Microelect Res Ctr, Atlanta, GA 30332 USA
关键词
interconnections; modeling; multilevel systems; system analysis and design; system-level interconnect prediction; three-dimensional (3-D) architecture; wire-length distribution;
D O I
10.1109/92.974905
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects, The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9 x increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits.
引用
收藏
页码:922 / 928
页数:7
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