A Compact On-interposer Passive Equalizer for Chip-to-chip High-speed Data Transmission

被引：0
|
作者：
Kim, Heegon [1 ]
Cho, Jonghyun [1 ]
Kim, Joohee [1 ]
Kim, Kiyeong [1 ]
Choi, Sumin [1 ]
Kim, Joungho [1 ]
Pak, Jun So [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, TERA Lab, Taejon 305701, South Korea
来源：
2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS | 2012年
关键词：
Inter-symbol Interference (ISI); On-interposer passive equalizer; Silicon-interposer; Wide-band; Wide I/O;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a new compact on-interposer passive equalizer was proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the coil-shaped on-interposer shunt metal line structure to produce the high-pass filter for loss compensation. This results in wide-band channel equalization and low power-consumption. Moreover, the compact coil-shaped structure of the proposed equalizer allows for wide I/O and high adjustability. The remarkable performance of the proposed compact on-interposer passive equalizer is successfully demonstrated by a frequency- and time-domain simulation of up to 10 Gbps.
引用
收藏
页码：95 / 98
页数：4
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