Performance and Reliability Analysis for VLSI Circuits Using 45nm Technology

被引：0

作者：

Rahul ^{[1
]}

Yadav, Ajeet Kumar ^{[1
]}

Al Ayubi, Herman ^{[1
]}

Rizvi, Navaid Z. ^{[1
]}

机构：

[1] Gautam Buddha Univ, Sch Informat & Technol, Greater Noida 201308, India

来源：

2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT) | 2016年

关键词：

CMOS; HCI; NBTI; PBTI; TDDB; EXPRESSIONS; CROSSTALK;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Performance and reliability analysis tests the VLSI circuits over a prolonged period of time at different conditions. Therefore, performance and reliability of an inverter circuit and two CMOS gate interconnect circuit, a combination of two inverters connected with an RC model as an interconnect structure has been analyzed. Reliability in VLSI circuits depends on hot carrier injection, negative biasing temperature instability, positive biasing temperature instability and time -dependent gate oxide breakdown. Reliability is analyzed by comparing power, delay and output voltage. The complete analysis is done using 45nm gpdk (generic process design kit) in Cadence Virtuoso

引用

页码：4612 / 4616

页数：5

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