Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression

被引：1

作者：

Kim, Dooyoung ^{[1
]}

Ansari, M. Adil ^{[1
]}

Jung, Jihun ^{[1
]}

Park, Sungju ^{[1
]}

机构：

[1] Hanyang Univ, Dept Comp Sci & Engn, Sa 3 Dong, Ansan, Gyeonggi Do, South Korea

来源：

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2016年 / 16卷 / 05期

基金：

新加坡国家研究基金会;

关键词：

Test data compression; code-based test data compression; scan chain reordering; low power testing; routing congestion; TIME;

D O I：

10.5573/JSTS.2016.16.5.582

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

引用

页码：582 / 594

页数：13

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