An Effective FPGA Placement Flow Selection Framework using Machine Learning

One of the most time consuming steps in the FPGA CAD flow is the placement problem which directly impacts the completion of the design flow. Accordingly, a routability driven FPGA placement contest was organized by Xilinx in ISPD 2016 to address this problem. Due to variations in the ISPD benchmark characteristics and heterogeneity of the FPGA architectures, as well as the different optimization strategies employed by different participating placers, placement algorithms that performed well on some circuits performed poorly on others. In this paper we propose a Machine -Learning (ML) framework that is capable of recommending the best FPGA placement algorithm within the CAD flow. Results obtained indicate that the ML framework is capable of selecting the correct flow with an 83% accuracy.