Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

被引:50
|
作者
Rao, Padmakumar R. [1 ]
Wang, Xinyang [1 ]
Theuwissen, Albert J. P. [1 ,2 ]
机构
[1] Delft Univ Technol, Elect Instrumentat Lab, Delft, Netherlands
[2] Harvest Imaging, Bree, Belgium
关键词
CMOS image sensors; gated-diodes; radiation hardness; STI; spectral response;
D O I
10.1016/j.sse.2008.04.023
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive too]. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to gamma-ray irradiation is Studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to gamma-ray irradiation. Results further Suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments. (C) 2008 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1407 / 1413
页数:7
相关论文
共 50 条
  • [21] High-performance, deep-submicron CMOS technologies
    Sugii, T
    Deura, M
    Nara, Y
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1996, 32 (01): : 85 - 93
  • [22] TECHNOLOGY DESIGN FOR HIGH-CURRENT AND ESD ROBUSTNESS IN A DEEP-SUBMICRON CMOS PROCESS
    AMERASEKERA, A
    CHAPMAN, RA
    IEEE ELECTRON DEVICE LETTERS, 1994, 15 (10) : 383 - 385
  • [23] Interconnect strategy in deep-submicron DRAM technology
    Wee, JK
    Kim, SH
    Park, YJ
    Kim, SJ
    Chung, JY
    PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS, 2000, : 345 - 348
  • [24] Power design challenges in deep-submicron technology
    Anis, M
    Massoud, Y
    PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3, 2003, : 1510 - 1513
  • [25] Energy efficient signaling in deep-submicron technology
    Ben Dhaou, I
    Parhi, KK
    Tenhunen, H
    VLSI DESIGN, 2002, 15 (03) : 563 - 586
  • [26] COPPER METALLIZATION TECHNOLOGY FOR DEEP-SUBMICRON ULSIS
    ARITA, Y
    AWAYA, N
    OHNO, K
    SATO, M
    MRS BULLETIN, 1994, 19 (08) : 68 - 74
  • [27] DEEP-SUBMICRON TECHNOLOGY FORCES FOUNDRY DEPENDENCE
    HAILEY, S
    ELECTRONIC DESIGN, 1995, 43 (07) : 66 - 66
  • [28] Challenges in the design of PLLS in deep-submicron technology
    Khalil, Waleed
    Bakkaloglu, Bertan
    RADIO DESIGN IN NANOMETER TECHNOLOGIES, 2006, : 241 - 285
  • [29] A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology
    Gersbach, Marek
    Maruyama, Yuki
    Trimananda, Rahmadi
    Fishburn, Matt W.
    Stoppa, David
    Richardson, Justin A.
    Walker, Richard
    Henderson, Robert
    Charbon, Edoardo
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (06) : 1394 - 1407
  • [30] Design innovations for multi-gigahertz-rate communication circuits with deep-submicron CMOS technology
    Kurisu, M
    Fukaishi, M
    Asazawa, H
    Nishikawa, M
    Nakamura, K
    Yotsuyanagi, M
    IEICE TRANSACTIONS ON ELECTRONICS, 1999, E82C (03): : 428 - 437