A low-cost hardware approach to dependability validation of IPs

It has been recognized that analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of transient faults. It has been proposed to carry out such an analysis using fault injections in a hardware prototype of the circuit under design. This paper reports on a low cost environment using such a flow, A simple FPGA-based development board is used to emulate the circuit and the execution results are analysed on a PC computer. A generic, scalable. approach is proposed to overcome the limitations of such a simple set-tip. Such an environment can for example allow a designer to perform efficient and low cost dependability analyses for IP blocks.