Performance Improved Multilevel Inverter with Selective Harmonic Elimination

被引：1

作者：

Mamatha, P. ^{[1
]}

Venkatesh, Challa ^{[1
]}

机构：

[1] Kakatiya Inst Technol & Sci, Dept Elect & Elect Engn, Warangal, Telangana, India

来源：

2017 INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRICAL, ELECTRONICS AND COMPUTING TECHNOLOGIES (ICRTEECT) | 2017年

关键词：

Multilevel inverter; Selective Harmonic Elimination (SHE); Total harmonic distortion (THD); CONVERTERS; TOPOLOGY; DRIVES; MODULATION; SWITCHES;

D O I：

10.1109/ICRTEECT.2017.24

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Various topologies of multilevel inverters have been proposed as a potential replacement for cascaded multilevel inverters in high-voltage, high-power applications as they can be extended to any number of voltage levels without introducing much more complexity to the control system. This paper discussed in detail about the application of selective harmonic elimination pulse-width modulation (SHE-PWM) technique for thirteen-level cascaded submultilevel inverters. The switching angles are computed so as to eliminate the predominant low harmonic orders from inverter output voltage such that the total harmonic distortion (THD) is a minimum. The modulation method presented is confirmed by MATLAB/Simulink software and the simulation results are discussed.

引用

页码：133 / 138

页数：6

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