A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS

被引:48
作者
Yu, Hairong [1 ]
Chang, Mau-Chung Frank [1 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
关键词
calibration; flash analog-to-digital converter (ADC); offset correction; source follower; unity-gain buffer;
D O I
10.1109/TCSII.2008.921596
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.
引用
收藏
页码:668 / 672
页数:5
相关论文
共 5 条
[1]   A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging [J].
Jiang, XC ;
Chang, MCF .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (02) :532-535
[2]  
Park S, 2006, IEEE CUST INTEGR CIR, P489
[3]   A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS [J].
Sandner, C ;
Clara, M ;
Santner, A ;
Hartig, T ;
Kuttner, F .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (07) :1499-1505
[4]   A distortion compensating flash analog-to-digital conversion technique [J].
Srinivas, Venkata ;
Pavan, Shanthi ;
Lachhwani, Ashish ;
Sasidhar, Naga .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (09) :1959-1969
[5]   A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency [J].
Taft, RC ;
Menkus, CA ;
Tursi, MR ;
Hidri, O ;
Pons, V .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2107-2115