Leakage Characterization of 10T SRAM Cell

被引：107

作者：

Islam, A. ^{[1
]}

Hasan, M. ^{[2
]}

机构：

[1] Birla Inst Technol, Dept Elect & Commun Engn, Ranchi 835215, Jharkhand, India

[2] Aligarh Muslim Univ, Dept Elect Engn, Aligarh 202002, Uttar Pradesh, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2012年 / 59卷 / 03期

关键词：

Read static noise margin (RSNM); SRAM; standby power; variability; POWER APPLICATIONS; HIGH-SPEED; CMOS; VARIABILITY; DESIGN;

D O I：

10.1109/TED.2011.2181387

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells.

引用

页码：631 / 638

页数：8

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