Reducing cache misses through cache line overlapping

被引：0

作者：

Koo, S

Kim, S

Azougagh, D

Cho, Y

Maeng, S

机构：

[1] Korea Adv Inst Sci & Technol, Dept EECS, Taejon 305701, South Korea

[2] Univ Suwon, Dept Comp Sci, Hwaseong 445743, South Korea

来源：

ELECTRONICS LETTERS | 2006年 / 42卷 / 10期

关键词：

D O I：

10.1049/el:20064195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

By studying the behaviour of general programmes, it was observed that over 50% of bytes in a data cache are zero-valued. To reduce this waste of zero-valued spaces in a data cache, an overlapped cache scheme, which allows one cache line entry to hold up to two cache lines, is proposed. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces cache misses by 29% on average over a conventional direct-mapped cache.

引用

页码：569 / 571

页数：3

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