Linear Doherty Power Amplifier With an Enhanced Back-Off Efficiency Mode for Handset Applications

This paper presents a linear Doherty power amplifier (PA) with enhanced back-off efficiency mode for handset applications. For linear Doherty operation, we analyze the gain modulation as well as the cancellation of the third-order intermodulation distortion in order to improve the linearity. A compact design method is also discussed to implement on a single chip for a handset. The proposed Doherty PA delivers good performance with regard to the third-generation (3G)/fourth-generation (4G) modulation signals. A switched-load power-mode PA is adopted in the proposed Doherty PA to enhance the efficiency in the low-power region with over 10-dB back-off. For demonstration purposes, the PA is implemented using an InGaP/GaAs heterojunction bipolar transistor and AlGaAs/InGaAs pseudomorphic high electron-mobility transistor process. The PA is tested at 1.85 GHz using both a long-term evolution signal with 16-quadrature amplitude modulation, 7.5-dB peak-to-average power ratio, and 10-MHz bandwidth (BW) and a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW. The proposed linear Doherty PA with an enhanced back-off efficiency mode delivers good performance in both the high-and low-power modes, implying that the dual-power-mode Doherty PA configuration can be a promising candidate for extending the battery life of handheld devices in 3G and 4G wireless communication systems.