A constant charging-current relaxation oscillator with a duty-cycled main comparator and an adaptive auxiliary comparator

A low-power constant charging-current relaxation oscillator that outputs a frequency-tunable sawtooth signal and a pulse signal is proposed and implemented in 0.5-mu m CMOS process. At the architecture level, two com-parators with 10 times difference in power consumption are proposed to break up the tight tradeoff between power consumption and oscillation performance. Most of the time, only the low-power auxiliary comparator works to save power. The high-power main comparator is controlled by the auxiliary comparator output and only works when a ramping voltage is close to a reference voltage. At the circuit level, an adaptive current control technique that makes current adversely proportional to input voltage differences is used to further reduce the power consumed in the low-power comparator. The measured clock phase noise at the offset frequency of 100 kHz is-115.07 dBc/Hz at the output frequency of 1 MHz. The measured output frequency variations are 124 ppm/degrees C over temperatures from-55 degrees C to 125 degrees C, and -0.13%-0.18% over power supplies from 3 V to 5.5 V. The frequency range from 200 kHz to 1350 kHz is achieved. The power consumption at the 1 MHz output frequency is 9.5 mu W, which is comparable with state-of-the-art designs in the literature.