Analysis of Static Noise Margin for 7T SRAM Cell Using 45 nm Technology

This paper presents the different types of analysis such as noise, voltage, read margin and write margin of Static Random Access Memory (SRAM) cell for high-speed application. To help overcome limits to the speed of conventional SRAMs, we have developed a read and write static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. Static Noise Margin (SNM) is the most important parameter for memory design. SNM, which affects both read and write margin, is related to the threshold voltages of the NMOS and PMOS devices of the SRAM cell that is why we have analyzed SNM with the Read Margin, Write Margin and also the Threshold voltage. We have fabricated various proposed 7T SRAM cell using 45-nm CMOS technology and have obtained with it a minimum VDD of 0.7 V and a 5-ns access time with a 0.7-V supply.