Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique

被引:18
作者
Ba, Papa-Sidy [1 ]
Dupuis, Sophie [1 ]
Palanichamy, Manikandan [1 ]
Marie-Lise-Flottes [1 ]
Di Natale, Giorgio [1 ]
Rouzeyre, Bruno [1 ]
机构
[1] Univ Montpellier, CNRS UMR 5506, LIRMM, Montpellier, France
来源
2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) | 2016年
关键词
Harware-Trojans; Design-for-Hardware-Trust; Layout; Placement and routing; THREAT;
D O I
10.1109/ISVLSI.2016.22
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The insertion of malicious alterations to a circuit, referred to as Hardware Trojans, is a threat considered more and more seriously during the last years. Numerous methods have been proposed in the literature to detect the presence of such alterations. More recently, Design-for-Hardware-Trust (DfHT) methods have been proposed, that enhance the design of the circuit in order to incorporate features that can either prevent the insertion of a HT or that can help detection methods. This paper focuses on a HT prevention technique that aims at creating a layout without filler cells, which are assumed to provide a great opportunity for HT insertion, in order to make the insertion of a HT in a layout as difficult as possible.
引用
收藏
页码:254 / 259
页数:6
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