Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers

被引：0

作者：

Shi, B ^{[1
]}

Sundström, L ^{[1
]}

机构：

[1] Univ Lund, Dept Appl Elect, Competence Ctr Circuit Design, SE-22100 Lund, Sweden

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an integrated circuit design and implementation of a simple and partly new RF power amplifier linearization system based on power feedback. The prototype linearization IC using a standard double-metal double-poly 0.8 mu m CMOS process was fabricated and tested. When it was used to linearize an efficient power amplifier transmitting a pi/4-shifted DQPSK modulated North American Digital Cellular (NADC) signal, experimental results showed that a reduction of more than 10dB in the adjacent channel interference was achieved. The chip, which occupies 1.9mm(2) with pads, operates with 5V supply voltage and measured power consumption is 65mW.

引用

页码：252 / 255

页数：2

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