Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

A yield estimation model to evaluate the lithography distortion in a printed layout is presented. The yield model relates the probability of non-failure of a lithography hotspot with the manufacturing yield loss. We define a lithography hotspot as a pattern construct with excessive variation under lithography printing using lithography simulations. Thereby, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho-degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the manufacturing yield and increases the number of good dies per wafer.