A 0.6 V Low-Power Wide-Range Delay-Locked Loop in 0.18 μm CMOS

被引：25
|
作者：
Lu, Chung-Ting [1 ,2 ]
Hsieh, Hsieh-Hung [1 ,2 ]
Lu, Liang-Hung [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2009年 / 19卷 / 10期
关键词：
Delay-locked loops (DLLs); forward-body bias; low-power; low-voltage; voltage-controlled delay cell;
D O I：
10.1109/LMWC.2009.2029752
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this letter, a delay-locked loop (DLL) suitable for low-power and low-voltage operations is presented. To overcome the performance limitations, such as a restricted locking range and elevated output jitters, a novel voltage-controlled delay cell and a phase/ frequency detector with a start controller are employed in the proposed DLL. Using a standard 0.18 mu m CMOS process, the fabricated circuit exhibits a locking range from 85 to 550 MHz. The measured peak-to-peak and rms jitters at 550 MHz are 25.6 and 3.8 ps, respectively. Operated at a supply voltage of 0.6 V, the power consumption of the DLL circuit varies from 2.4 to 4.2 mW within the entire locking range.
引用
收藏
页码：662 / 664
页数：3
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