Pad Deflection-Based Model of Chemical-Mechanical Polishing for Use in CAD IC Layout

被引：4

作者：

Comes, Ryan B. ^{[1
]}

Terrell, Elon J. ^{[2
]}

Higgs, C. Fred, III ^{[3
]}

机构：

[1] Univ Virginia, Charlottesville, VA 22904 USA

[2] Columbia Univ, Dept Mech Engn, New York, NY 10027 USA

[3] Carnegie Mellon Univ, Dept Mech Engn, Pittsburgh, PA 15213 USA

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 2010年 / 23卷 / 01期

基金：

美国国家科学基金会;

关键词：

Chemical-mechanical polishing (CMP); design for manufacturability; metal interconnect; PLANARIZATION; IMPACT;

D O I：

10.1109/TSM.2009.2039182

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The use of chemical-mechanical polishing (CMP) during the integrated circuit (IC) fabrication process has allowed for the aggressive interconnect patterning that is necessary for modern microprocessor technology. However, as IC technology has moved into the deep submicron realm, nonidealities during polishing have begun to play a significant role in device yield and circuit performance. In order to accurately predict circuit performance, designers must consider the effects of CMP prior to fabrication. A physics-based model to predict feature-scale wear of devices during polishing is presented and integrated into a CAD framework to test the model on various IC layouts. The model is benchmarked against experimental data and shown to be qualitatively accurate in predicting surface topography evolution.

引用

页码：121 / 131

页数：11

共 38 条

[1] CAI H, 2007, THESIS MIT BOSTON
[2] CAI H, 2004, P MRS SPRING M S K C, P63
[3] Campbell S A, 2001, SCI ENG MICROELECTRO
[4] A locally relevant Prestonian model for wafer polishing
Castillo-Mejia, D
Beaudoin, S
[J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2003, 150 (02) : G96 - G102
[5] Wear-contact problems and modeling of chemical mechanical polishing
Chekina, OG
Keer, LM
Liang, H
[J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1998, 145 (06) : 2100 - 2106
[6] Analysis of the impact of proximity correction algorithms on circuit performance
Chen, L
Milor, LS
Ouyang, CH
Maly, W
Peng, YK
[J]. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1999, 12 (03) : 313 - 322
[7] Hierarchical dummy fill for process uniformity
Chen, Y
Kahng, AB
Robins, G
Zelikovsky, A
[J]. PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 139 - 144
[8] An empirical dielectric erosion formula in metal chemical mechanical planarization
Chen, Z
Sun, F
Vacassy, R
[J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2006, 153 (06) : G582 - G586
[9] Chip scale topography evolution model for CMP process optimization
Choi, J
Dornfeld, DA
[J]. ISSM 2005: IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2005, : 430 - 433
[10] Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing
Choi, Munkang
Milor, Linda
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (07) : 1350 - 1367

← 1 2 3 4 →