FPGA test and coverage

被引：37

作者：

Toutounchi, S

Lai, A

机构：

[1] San Jose, CA 95124

来源：

INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/TEST.2002.1041811

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents FPGA test and coverage methodology. BIST and "shift register" styles of test is discussed. Gate level fault grading results are then presented. Use of "iterative logic unit" and its impact on test and fault grading is discussed.

引用

页码：599 / 607

页数：9

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