DESIGN AND FPGA IMPLEMENTATION OF DIGITAL PULSE COMPRESSION FOR BAND-PASS RADAR SIGNALS

被引:5
作者
Golubicic, Zoran [1 ]
Simic, Slobodan [2 ]
Zejak, Aleksa J. [3 ]
机构
[1] Univ Def, Dept Elect Syst, Belgrade, Serbia
[2] RT RK Comp Based Syst, Novi Sad, Serbia
[3] Peripolis Elekt, Belgrade, Serbia
来源
JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS | 2013年 / 64卷 / 03期
关键词
digital down converter; digital pulse compression; FPGA mismatched filter; sidelobes reduction; REAL-TIME IMPLEMENTATION; CORRELATOR; SYSTEMS;
D O I
10.2478/jee-2013-0028
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The paper presents fully digitized approach for band-pass discrete coded radar signals. The emphasis is to use one generalized reconfigurable compressor for several different types of signals and different types of receivers. It fits for direct radio frequency receiver (RF) as well as for intermediate frequency (IF) receiver. The system implementation on field programmable gate area (FPGA) let us eliminate special chips previously needed. From the experimental results it is known that this approach appears to work well for matched and mismatched pulse compression and it outstands when time-bandwidth product (TB) is of order 1000. A precision of 14 bits has been considered in the input signal and 16 bits in the filter coefficients. It gives the dynamic range of 78 dB and the quantification error less than 0.012 %.
引用
收藏
页码:191 / 195
页数:5
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