Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

被引：18

作者：

Caffarena, Gabriel ^{[1
]}

Constantinides, George A.

Cheung, Peter Y. K.

Carreras, Carlos

Nieto-Taladriz, Octavio

机构：

[1] Univ Politecn Madrid, Dept Ingn Elect, E-28040 Madrid, Spain

[2] Univ London Imperial Coll Sci Technol & Med, Dept Elect & Elect Engn, London SW7 2BT, England

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2006年 / 53卷 / 05期

基金：

英国工程与自然科学研究理事会;

关键词：

architectural synthesis; digital signal processing; fixed-point arithmetic; word-length allocation;

D O I：

10.1109/TCSII.2005.862175

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, we address the combined application of word-length allocation and architectural synthesis of linear time-invariant digital signal processing systems. These two design tasks are traditionally performed sequentially, thus lessening the overall design complexity, but ignoring forward and backward dependencies that may lead to cost reductions. Mixed integer linear programming is used to formulate the combined problem and results are compared to the two-step traditional approach.

引用

页码：339 / 343

页数：5