Wafer Test Methods to Improve Semiconductor Die Reliability

被引：5
|
作者：
Mann, William R.
机构：
[1] Rockwell International, Newport Beach, CA 92663
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2008年 / 25卷 / 06期
关键词：
Performance evaluation; Process control; Reliability; Reliability engineering; Robustness; Semiconductor device reliability; Testing;
D O I：
10.1109/MDT.2008.174
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Incremental advances in semiconductor device testing have improved device quality and reliability. New test methods applied to dies at the wafer level are now significantly improving the reliability of devices sold to the increasing bare-die market and reducing burn-in requirements for packaged devices.
引用
收藏
页码：528 / 537
页数：10
相关论文
共 50 条
  • [21] Silicon wafer orientation dependence of metal oxide semiconductor device reliability
    Nakamura, Kou, 1600, Publ by JJAP, Minato-ku, Japan (33):
  • [22] Intelligent Methods for Test and Reliability
    Amrouch, H.
    Anders, J.
    Becker, S.
    Betka, M.
    Bleher, G.
    Domanski, P.
    Elhamawy, N.
    Ertl, T.
    Gatzastras, A.
    Genssler, P.
    Hasler, S.
    Heinrich, M.
    van Hoorn, A.
    Jafarzadeh, H.
    Kallfass, I
    Klemme, F.
    Koch, S.
    Kuesters, R.
    Lalama, A.
    Latty, R.
    Liao, Y.
    Lylina, N.
    Haghi, Z. Najafi
    Pflueger, D.
    Polian, I
    Rivoir, J.
    Sauer, M.
    Schwachhofer, D.
    Templin, S.
    Volmer, C.
    Wagner, S.
    Weiskopf, D.
    Wunderlich, H-J
    Yang, B.
    Zimmermann, M.
    PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, : 969 - 974
  • [23] Study on Reliability Test of Die Attach Material
    Yik, Lim Chuan
    Kar, Yap Boon
    Shafika, Nor
    2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT), 2012,
  • [24] HOW TO USE FAILURE ANALYSIS TO IMPROVE SEMICONDUCTOR RELIABILITY
    MUNCHERY.HM
    ELECTRONIC ENGINEER, 1968, 27 (05): : 49 - &
  • [25] Drop test reliability of wafer level chip scale packages
    Alajoki, M
    Nguyen, L
    Kivilahti, J
    55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 637 - 644
  • [26] Die/wafer Sub-micron Alignment Strategies for Semiconductor Device Integration
    Shea-Rohwer, Lauren E.
    Martin, James E.
    Chu, Dahwey
    SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS, 2011, 35 (02): : 153 - 162
  • [27] Test methods for silicon die strength
    Tsai, M. Y.
    Chen, C. H.
    Lin, C. S.
    JOURNAL OF ELECTRONIC PACKAGING, 2006, 128 (04) : 419 - 426
  • [28] Novel test methods for die strength
    Tsai, M. Y.
    Chen, C. H.
    Lin, C. S.
    ADVANCES IN ELECTRONIC PACKAGING 2005, PTS A-C, 2005, : 939 - 945
  • [29] A DIRECTED-GRAPH CLASSIFIER OF SEMICONDUCTOR WAFER-TEST PATTERNS
    CRESSWELL, MW
    KHERA, D
    LINHOLM, LW
    SCHUSTER, CE
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1992, 5 (03) : 255 - 263
  • [30] Hybrid Feature Selection for Wafer Acceptance Test Parameters in Semiconductor Manufacturing
    Xu, Hongwei
    Zhang, Jie
    Lv, Youlong
    Zheng, Peng
    IEEE ACCESS, 2020, 8 : 17320 - 17330
12345