A low-power A/D conversion technique using correlation of moving pictures

被引:0
|
作者
Kawahito, S [1 ]
Naka, J [1 ]
Tadokoro, Y [1 ]
机构
[1] Toyohashi Univ Technol, Dept Informat & Comp Sci, Toyohashi, Aichi 4418580, Japan
关键词
A/D converter; low-power design; CMOS image sensor; moving picture correlation;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.
引用
收藏
页码:1764 / 1771
页数:8
相关论文
共 50 条
  • [31] Low-Power High-Accuracy Approximate Multiplier Using Approximate High-Order Compressors
    Tung, Che-Wei
    Huang, Shih-Hsu
    PROCEEDINGS OF 2019 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION ENGINEERING AND TECHNOLOGY (ICCET 2019), 2019, : 163 - 167
  • [32] A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique
    Lin, Jin-Fu
    Chang, Soon-Jyh
    Liu, Chun-Cheng
    Huang, Chih-Hao
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (03) : 163 - 167
  • [33] Design of high-Q varactors for low-power wireless applications using a standard CMOS process
    Porret, AS
    Melly, T
    Enz, CC
    Vittoz, EA
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (03) : 337 - 345
  • [34] A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
    Niitsu, Kiichi
    Kawai, Shusuke
    Miura, Noriyuki
    Ishikuro, Hiroki
    Kuroda, Tadahiro
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (07) : 1285 - 1294
  • [35] A Low-Power 10-bit Single-Slope ADC Using Power Gating and Multi-Clocks for CMOS Image Sensors
    Jeon, Byoung-Kwan
    Hong, Seong-Kwan
    Kwon, Oh-Kyong
    2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 257 - 258
  • [36] An in-probe low-noise low-power variable-gain receive amplifier for medical ultrasound imaging using CMUT transducers
    Hourieh Attarzadeh
    Trond Ytterdal
    Analog Integrated Circuits and Signal Processing, 2017, 91 : 73 - 81
  • [37] An in-probe low-noise low-power variable-gain receive amplifier for medical ultrasound imaging using CMUT transducers
    Attarzadeh, Hourieh
    Ytterdal, Trond
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 91 (01) : 73 - 81
  • [38] Low-Power Cross-Layer Error Management Using MIMO-LDPC Iterative Decoding for Video Processing
    Yang, Yoon Seok
    Kim, Yongtae
    IEEE ACCESS, 2021, 9 : 133062 - 133075
  • [39] Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation
    Macko, Dominik
    Jelemenska, Katarina
    Cicak, Pavel
    INTEGRATION-THE VLSI JOURNAL, 2018, 63 : 101 - 114
  • [40] A low-power design method for FPGA using extra flip-flops driven by phase-shifted clock
    Katashita, Toshihiro
    Maeda, Atsushi
    Yamaguchi, Yoshinori
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 2007, 90 (08): : 35 - 44