A low-power A/D conversion technique using correlation of moving pictures

被引:0
|
作者
Kawahito, S [1 ]
Naka, J [1 ]
Tadokoro, Y [1 ]
机构
[1] Toyohashi Univ Technol, Dept Informat & Comp Sci, Toyohashi, Aichi 4418580, Japan
关键词
A/D converter; low-power design; CMOS image sensor; moving picture correlation;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.
引用
收藏
页码:1764 / 1771
页数:8
相关论文
共 50 条
  • [1] Low-power design technique with ambipolar double gate devices
    Jabeur, Kotb
    O'Connor, Ian
    Navarro, David
    Le Beux, Sebastien
    PROCEEDINGS OF THE 2012 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2012, : 14 - 21
  • [2] An efficient low-swing multithreshold-voltage low-power design technique
    Rjoub, A
    Alrousan, M
    Aljarrah, O
    Koufopavlou, O
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2004, 13 (01) : 193 - 203
  • [3] A Low-Power Parallel-to-Serial Conversion Circuit for CMOS Image Sensors
    Zhang Jicun
    Chen Nan
    Liu Chuanming
    Yao Libin
    PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
  • [4] Low-power design of high-speed A/D converters
    Kawahito, S
    Honda, K
    Furuta, M
    Kawai, N
    Miyazaki, D
    IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (04): : 468 - 478
  • [5] Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack
    Vosoughi, M. Ali
    Wang, Longfei
    Kose, Selcuk
    2019 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP), 2019,
  • [6] Low-power design for DC current transformer using class-D compensating amplifier
    Veinovic, Slavko
    Ponjavic, Milan
    Milic, Sasa
    Djuric, Radivoje
    IET CIRCUITS DEVICES & SYSTEMS, 2018, 12 (03) : 215 - 220
  • [7] Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
    Namin, Shoaleh Hashemi
    Wu, Huapeng
    Ahmadi, Majid
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (02) : 441 - 449
  • [8] Low-power area-efficient pipelined A/D converter design using a single-ended amplifier
    Miyazaki, D
    Kawahito, S
    Tadokoro, Y
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (02) : 293 - 300
  • [9] Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier
    Daisuke Miyazaki
    Shoji Kawahito
    Analog Integrated Circuits and Signal Processing, 2000, 25 : 235 - 244
  • [10] Low-power area-efficient pipelined A/D converter design using a single-ended amplifier
    Miyazaki, D
    Kawahito, S
    Tadokoro, Y
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2000, 25 (03) : 235 - 244