Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme

被引：16

作者：

Chiang, Cheng-Hao ^{[1
]}

Kuo, Li-Min ^{[2
]}

Hu, Yu-Chen ^{[1
]}

Huang, Wen-Chun ^{[1
]}

Ko, Cheng-Ta ^{[1
]}

Chen, Kuan-Neng ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Dept Electrophys, Hsinchu 300, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2013年 / 34卷 / 05期

关键词：

3-D integration; bottom-up plating; through-silicon via (TSV);

D O I：

10.1109/LED.2013.2250249

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.

引用

页码：671 / 673

页数：3

共 10 条

[1]

[Anonymous], 2001, INT TECHNOLOGY ROADM

[2]

[Anonymous], 2012, PROC 2011 IEEE INT 3

[3]

[Anonymous], IEEE P EL COMP TECHN

[4]

[Anonymous], P IEEE 4 INT MICR PA

[5] TSV Process Using Bottom-up Cu Electroplating and its Reliability Test [J].

Chang, H. H. ;

Shih, Y. C. ;

Hsu, C. K. ;

Hsiao, Z. C. ;

Chiang, C. W. ;

Chen, Y. H. ;

Chiang, K. N. .

ESTC 2008: 2ND ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, :645-+

[6]

Jourdain A, 2011, ELEC COMP C, P1122, DOI 10.1109/ECTC.2011.5898650

[7]

Katti G., 2009, 2009 IEEE INT ELECT, P1

[8] Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs [J].

Katti, Guruprasad ;

Stucchi, Michele ;

De Meyer, Kristin ;

Dehaene, Wim .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (01) :256-262

[9] Via First Approach Optimisation for Through Silicon Via Applications [J].

Laviron, Cyrille ;

Dunne, Brendan ;

Lapras, Valerie ;

Galbiati, Paola ;

Henry, David ;

Toia, Fabrizio ;

Moreau, Stephane ;

Anciant, Romain ;

Brunet-Manquat, Cahty ;

Sillon, Nicolas .

2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, :14-+

[10] Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects [J].

Yu, Aibin ;

Lau, John H. ;

Ho, Soon Wee ;

Kumar, Aditya ;

Hnin, Wai Yin ;

Lee, Wen Sheng ;

Jong, Ming Ching ;

Sekhar, Vasarla Nagendra ;

Kripesh, Vaidyanathan ;

Pinjala, Damaruganath ;

Chen, Scott ;

Chan, Chien-Feng ;

Chao, Chun-Chieh ;

Chiu, Chi-Hsin ;

Huang, Chih-Ming ;

Chen, Carl .

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (09) :1336-1344

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