Wafer-level 3D integration technology

被引：143

作者：

Koester, S. J. ^{[1
]}

Young, A. M. ^{[1
]}

Yu, R. R. ^{[1
]}

Purushothaman, S. ^{[1
]}

Chen, K. -N. ^{[1
]}

La Tulipe, D. C., Jr. ^{[1
]}

Rana, N. ^{[1
]}

Shi, L. ^{[1
]}

Wordeman, M. R. ^{[1
]}

Sprogis, E. J. ^{[2
]}

机构：

[1] IBM Corp, Div Res, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

[2] IBM Corp, Syst & Technol Grp, Essex Jct, VT 05452 USA

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2008年 / 52卷 / 06期

关键词：

D O I：

10.1147/JRD.2008.5388565

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

引用

页码：583 / 597

页数：15

共 35 条

[1] A CMOS-compatible process for fabricating electrical through-vias in silicon [J].

Andry, P. S. ;

Tsang, C. ;

Sprogis, E. ;

Patel, C. ;

Wright, S. L. ;

Webb, B. C. ;

Buchwalter, L. P. ;

Manzer, D. ;

Horton, R. ;

Polastre, R. ;

Knickerbocker, J. .

56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, :831-+

[2] A wafer-scale 3-D circuit integration technology [J].

Burns, James A. ;

Aull, Brian F. ;

Chen, Chenson K. ;

Chen, Chang-Lee ;

Keast, Craig L. ;

Knecht, Jeffrey M. ;

Suntharalingam, Vyshnavi ;

Warner, Keith ;

Wyatt, Peter W. ;

Yost, Donna-Ruth W. .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (10) :2507-2516

[3] Morphology and bond strength of copper wafer bonding [J].

Chen, KN ;

Tan, CS ;

Fan, A ;

Reif, R .

ELECTROCHEMICAL AND SOLID STATE LETTERS, 2004, 7 (01) :G14-G16

[4]

CHEN KN, 2006, P INT EL DEV M SAN F, P20

[5]

CHEN KN, 2006, P 23 INT VLSI MULT I, P195

[6] Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink [J].

Dang, B ;

Bakir, MS ;

Meindl, JD .

IEEE ELECTRON DEVICE LETTERS, 2006, 27 (02) :117-119

[7] DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].

DENNARD, RH ;

GAENSSLEN, FH ;

YU, HN ;

RIDEOUT, VL ;

BASSOUS, E ;

LEBLANC, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268

[8]

Emma P, 2006, INTEGR CIRCUIT SYST, P235, DOI 10.1007/978-0-387-34047-0_10

[9]

GERTY D, 2007, P 13 INT WORKSH THER

[10]

GUARINI KW, 2005, P 6 ANN INT C MICR I, P212

← 1 2 3 4 →