Characterization of single-sided gate-to-drain non-overlapped implantation nMOSFETs for multi-functional non-volatile memory applications

被引：5

作者：

Jeng, E. S. ^{[1
]}

Chen, Y. F. ^{[2
,3
]}

Chang, C. C. ^{[1
]}

Peng, K. M. ^{[1
]}

Chou, S. W. ^{[1
]}

Ho, C. W. ^{[1
]}

Huang, C. F. ^{[3
]}

Gong, J. ^{[4
]}

机构：

[1] Chung Yuan Christian Univ, Dept Elect Engn, Chungli, Taiwan

[2] Appl Intellectual Properties Ltd, Taipei, Taiwan

[3] Natl Tsing Hua Univ, Inst Elect Engn, Hsinchu, Taiwan

[4] Tunghai Univ, Dept Elect Engn, Taichung 40704, Taiwan

来源：

SOLID-STATE ELECTRONICS | 2012年 / 68卷

关键词：

Non-overlapped implantation; Charge-trapping; Antifuse; Mask ROM; EEPROM; SPACERS; CELL; ROM;

D O I：

10.1016/j.sse.2011.09.012

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Novel single-sided non-overlapped implantation (SNOI) nMOSFETs are characterized for their capability of multiple programmable memory functions. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using a pure logic processing. To function as mask ROMs, they can be mask-coded with the source drain extension (SDE) implantation. They can also be used as EEPROM devices by trapping charges in the side-wall nitride spacers. Furthermore, SNOI devices can be used as antifuses by introducing the punch-through stress at the drain side. The SNOI devices were successfully demonstrated for antifuse operations with an extremely high program/initial readout current ratio exceeding 10(9) and a program speed as high as 1 mu s. These novel SNOI devices not only provide non-volatile memory solutions in standard CMOS processing but also give a flexible choice among mask ROM, antifuse and EEPROM functions. (C) 2011 Elsevier Ltd. All rights reserved.

引用

页码：73 / 79

页数：7

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