The flipped voltage follower-based low voltage fully differential CMOS sample-and-hold circuit

被引:2
|
作者
Fayomi, Christian Jesus B. [1 ]
Ramirez-Angulo, Jamine [2 ]
Wirth, Gilson I. [3 ]
Matsuzawa, Akira [4 ]
机构
[1] Univ Quebec Montreal, Comp Sc Dept, Wireless Smart Dev Labs, Montreal, PQ, Canada
[2] New Mexico State Univ, Klipsch Sch Elect & Comp Engn, Las Cruces, NM 88003 USA
[3] Univ Fed Rio Grande do Sul, Dept Elect Engn, Porto Alegre, RS, Brazil
[4] Tokyo Inst Technol, Dept Phys Elect, Tokyo, Japan
来源
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年
基金
加拿大自然科学与工程研究理事会;
关键词
D O I
10.1109/ISCAS.2008.4541768
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents the design and preliminary results of a full differential sample-and-hold circuit based on the "flipped voltage follower" (FVF) cell. The heart of this circuit is a fully differential low-voltage OTA based on FVF technique. The use of the FVF reduces the supply power requirements in the OTA. To overcome input sampling switches limitation imposed by the low supply voltage we make use of a low-voltage low stress an reliable clock signal doubler. It is evidenced how different versions of theses cells, coined as "flipped voltage follower (FVF)" and voltage doubler have been used in the past for many applications Preliminary simulation results in a 0.18 pin digital CMOS process show that a resolution greater than 8 bits can be obtained with a 1.0 V supply voltage using a 1 MHz clock signal. Further investigations on the performance limit of the proposed method as well as reliability concerns will be performed on the experimental test chip.
引用
收藏
页码:1716 / +
页数:2
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