The flipped voltage follower-based low voltage fully differential CMOS sample-and-hold circuit

This paper presents the design and preliminary results of a full differential sample-and-hold circuit based on the "flipped voltage follower" (FVF) cell. The heart of this circuit is a fully differential low-voltage OTA based on FVF technique. The use of the FVF reduces the supply power requirements in the OTA. To overcome input sampling switches limitation imposed by the low supply voltage we make use of a low-voltage low stress an reliable clock signal doubler. It is evidenced how different versions of theses cells, coined as "flipped voltage follower (FVF)" and voltage doubler have been used in the past for many applications Preliminary simulation results in a 0.18 pin digital CMOS process show that a resolution greater than 8 bits can be obtained with a 1.0 V supply voltage using a 1 MHz clock signal. Further investigations on the performance limit of the proposed method as well as reliability concerns will be performed on the experimental test chip.