Selective Fault Tolerance by Counting Gates with Controlling Value

The protection of flip-flops against soft errors in digital circuits incurs significant overheads. To reduce the protection costs, it is common to identify the flip-flops in which errors can produce an effect on the system output or a persistent error in its state. Then, only those critical flip-flops are protected. To identify those flip-flops, one option is to perform fault injection on all the flips flops during functional simulations but this does not scale well for large circuits as the time required to perform an evaluation would not be practical. Another option is to perform the identification based only on the structural properties of the circuit. For example, flip-flops that are in loops are more likely to produce persistent errors and those closer to the system outputs to affect them. In this paper, an enhancement to the structural analysis is proposed to improve its accuracy. The idea is to identify gates that can mask error propagation as they have a controlling value and use only those to measure distances on the circuit to estimate the criticality of flip-flops. This enables us to better predict the effect of errors while keeping the analysis simple and based only on structural properties and gate types. The proposed scheme has been implemented and tested on a realistic circuit to show its effectiveness.