Design space exploration of low-power flip-flops in FinFET technology

As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor sizing methods in FinFET technology to design the FF circuit based on different input and output capacitances. The results indicate that the circuit designed using minimum-energy-delay-area product (min-EDAP) approach has the lowest PDP. We developed a modified logical effort approach that leads to a minimum EDP design compared to the other approaches. The performance of flip-flop is also investigated based on the metrics extracted from energy efficient curve (EEC). Results show that the ED metric has the minimum EDP in all cases. Moreover, the E 4 D metric shows the least variations against frequency and voltage fluctuations, while the ED 4 metric is more robust against temperature variations. Simulations are performed using HSPICE in 16 nm FinFET technology with shorted-gate (SG) mode configuration.