Investigation of the Low Temperature/High Temperature approach to produce Si0.5Ge0.5 and Ge Strain Relaxed Buffers

We have checked whether or not the Low Temperature / High Temperature approach used for pure Ge growth on Si yielded high quality Si0.5Ge0.5 Strain-Relaxed Buffers (SRBs) that could serve afterwards as templates for thick Ge layers. We had, as soon as the Si0.48Ge0.52 layers grown at 550 degrees C plastically relaxed, a surface roughening which was not recovered by the 850 degrees C growth of Si0.5Ge0.5 (rms roughness: 5 nm). Thickening it with Ge at 750 degrees C and using a Thermal Cycling yielded a slight surface roughness decrease, however (down to 4 nm). The HT Si0.5Ge0.5 and pure Ge layers were slightly tensile strained. This was due to thermal expansion coefficient differences between Si and SiGe (Ge) coming into play during the cooling-down to room temperature. We had otherwise used the Ayers' theory in order to transform the full widths at half maximum of SiGe and Ge X-Ray Diffraction omega scans into Threading Dislocations Densities. We would then have, for 60 degrees misfit dislocations in our stacks, the following values: 3.5x10(8) cm(-2) in annealed 1.7 mu m thick Si0.5Ge0.5 SRBs and 1.6x10(8) cm(-2) in the 1.3 mu m thick Ge layers on top. Those values were definitely higher than those in 1.4 mu m thick, cyclically annealed pure Ge layers grown directly on Si and in the top part of similar to 6 mu m thick Si0.5Ge0.5 linearly graded virtual substrates.