0.7-V supply, 21-nW All-MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS

被引:22
作者
Aminzadeh, Hamed [1 ]
Valinezhad, Mohammad Mahdi [1 ]
机构
[1] Payame Noor Univ, Dept Elect Engn, Tehran 193953697, Iran
来源
MICROELECTRONICS JOURNAL | 2020年 / 102卷
关键词
Line regulation; Low power; MOS-Only; Resistorless; Temperature compensation; And voltage reference; SUBTHRESHOLD VOLTAGE; BANDGAP REFERENCE;
D O I
10.1016/j.mejo.2020.104841
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A nano-power all-MOS voltage reference circuit is proposed without any integrated resistor or bipolar transistor to generate multiple voltage sources in inexpensive digital CMOS technologies. The design is based on a current-driven voltage reference core made by standard nMOS transistors only, and can be powered up by a flexible biasing current with no consideration on its temperature characteristics. The sensitive core is shielded from the unregulated voltage supply via a voltage follower MOS transistor, whose gate terminal is driven by a supply-insensitive voltage source coming from the internal biasing configuration. The additional voltage reference is generated using the type of the biasing current made by the main voltage reference loaded by a transistor. A MOS-only implementation of the proposed reference employs MOS devices instead of passive resistors and linear capacitors. A prototype of the proposed solution consumes 30 nA with an area of 0.01 mm(2) in 0.18-mu m CMOS process, producing a main voltage reference of 147 mV while operating at the supply voltage down to 0.7 V. Simulation results demonstrate an average temperature coefficient (TC) of 66.38 ppm/degrees C for a temperature range of -40 to 120 degrees C. The line sensitivity is about 0.031%/V for the line voltages above 1.3 V. The mean power supply rejection ratio (PSRR) is -90 dB and -64.4 dB at 10 Hz and 1 MHz, respectively, when the voltage supply is set to 1.8 V and an equivalent MOS capacitor of 5 pF is used at the output. The 1% start-up settling time is 240 mu s for a 1.0 V voltage supply step, and can be reduced by increasing the supply voltage magnitude.
引用
收藏
页数:10
相关论文
共 41 条
[1]   A Sub-kT/q Voltage Reference Operating at 150 mV [J].
Albano, Domenico ;
Crupi, Felice ;
Cucchi, Francesca ;
Iannaccone, Giuseppe .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (08) :1547-1551
[2]   An All-MOSFET Voltage Reference With-50-dB PSR at 80 MHz for Low-Power SoC Design [J].
Alhassan, Nashiru ;
Zhou, Zekun ;
Sanchez-Sinencio, Edgar .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64 (08) :892-896
[4]   Low-dropout voltage reference: an approach to low-temperature-sensitivity architectures with high drive capability [J].
Aminzadeh, H. ;
Lotfi, R. ;
Mafinezhad, K. .
ELECTRONICS LETTERS, 2009, 45 (24) :1200-U17
[5]   Low-cost area-efficient low-dropout regulators using MOSFET capacitors [J].
Aminzadeh, Hamed ;
Lotfi, Reza ;
Mafinezhad, Khalil .
IEICE ELECTRONICS EXPRESS, 2008, 5 (16) :610-616
[6]   Low-Dropout Voltage Source: An Alternative Approach for Low-Dropout Voltage Regulators [J].
Aminzadeh, Hamed ;
Nabavi, Mohammad R. ;
Serdijn, Wouter A. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61 (06) :413-417
[7]   A low-supply-voltage CMOS sub-bandgap reference [J].
Becker-Gomez, Adriana ;
Viswanathan, T. Lakshmi ;
Viswanathan, T. R. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2008, 55 (07) :609-613
[8]   A CMOS bandgap reference without resistors [J].
Buck, AE ;
McDonald, CL ;
Lewis, SH ;
Viswanathan, TR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (01) :81-83
[9]  
Chen Hou-Ming, 2017, IEEE T CIRCUITS SYST, V64
[10]   A 0.12-0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems [J].
de Oliveira, Arthur Campos ;
Cordova, David ;
Klimach, Hamilton ;
Bampi, Sergio .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (11) :3790-3799