Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor

In this work, an InGaAs/GaAsSb-based p-type gate-all-around (GAA) arch-shaped tunneling field-effect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. The device performance was investigated in views of the on-state current (I-on), subthreshold swing (SS), and I-on/I-off ratio. For high current drivability, InGaAs/GaAsSb heterojunction is used to form the broken bandgap. Owing to the GAA arch-shaped structure of the TFET, the tunneling region between source and channel extended, thus I-on and SS are improved. However, it has some performance variations that are related with the height of the source region (H-source), the epitaxially grown thickness of the channel (t(epi)), and the height of the drain region (H-drain). Therefore, we performed a design optimization of the proposed device with the variables of H-source, t(epi), and H-drain. The designed and optimized InGaAs/GaAsSb-based p-type GAA arch-shaped TFET demonstrated an I-on of 215 mu A/mu m SS of 18 mV/dec and Ion/Ioff of 1.64x10(12).